As technology scales down CNTFET (Carbon Nano Tube Field Effect Transistor) circuits has gained importance in VLSI design due to exacerbation of process parameter variations

in CMOS. Particularly design of SRAM cell needs more attention as it occupies the larger space in CPU of the battery powered wearable devices. Hence it is a challenging task to the chip designer because the power, energy, speed and stability of the memory cell has a greater impact on system CPU efficiency. A variation tolerant nine transistor CNTFET SRAM cell is proposed in this work. Metrics considered for investigating the proposed SRAM performance is power, delay, power delay product (PDP) and static noise margin (SNM). Stanford University 32 nm CNTFET model and HSPICE tool is utilised for the simulation. In proposed SRAM the read and write power reduction is improved by 4.7x and 9.9x respectively, while the read delay and PDP reduction is improved by 10x than conventional SRAM. The hold, read and write stability of proposed memory cell is enhanced by 1.4x, 1.2x and 4.1x respectively compared to conventional structure.