A low-power 3-transistor (3T) approximate full adder based on CNFET technology is proposed for edge image processing applications requiring low computational cost and compact

area. The design emphasizes high power efficiency through an ultra-minimal transistor structure, which reduces circuit complexity while maintaining acceptable accuracy. Circuit-level performance is evaluated using a 32 nm CNFET model in the HSPICE simulator at a supply voltage of 0.9 V. The analysis considers key metrics such as power dissipation, propagation delay, power-delay product (PDP), and energy delay product (EDP). Results indicate power savings of about 35–40% and a delay reduction of approximately 55–60% compared to conventional approximate adders. Additionally, PDP improves by 75–80%, and EDP shows up to 90% enhancement. These improvements are mainly due to reduced transistor count and simplified routing paths. Although the design introduces approximation, the resulting accuracy remains within acceptable limits for error-tolerant image processing tasks. Overall, the proposed 3T CNFET full adder achieves an effective balance between power, delay, area, and computational accuracy.