In order to improve operational efficiency for lowpower VLSI (Very Large Scale Integration) designs, the current research presents a simulation-based comparison of the results

of basic gates, computation-intensive circuits, and basic memory blocks designed using FinFET technology. This creative designs in multipliers effectively consolidates input data by stacking blocks, which significantly reduces time in next-stage operations. To assess the suggested compressor design in terms of average power, delay, and Power Delay Product (PDP), extensive simulations and analyses are carried out. When conducted within the same technological and environmental conditions as existing designs, proposed designes demonstrate clear advantages. The proposed compressor shows an amazing 64.91% decrease in delay, a significant 87.85% improvement in average power consumption, and a notable 95.74% improvement in energy efficiency for proposed 4-3 compressor and similar outcomes for 5-3 compressor. In memory design, it also demonstrates a notable enhancement, achieving an 87.95% reduction in average power, a 49.57% decrease in delay, and an 87.57% improvement in Energy Delay Product (EDP) compared to both conventional NAND-based and FinFET-based Content Addressable Memory (CAM) designs.