{"id":1070,"date":"2026-08-16T21:40:35","date_gmt":"2026-08-16T21:40:35","guid":{"rendered":"https:\/\/els-journal.net\/wp\/about\/"},"modified":"2026-08-16T21:41:24","modified_gmt":"2026-08-16T21:41:24","slug":"30201-low-power-cntfet-3-transistor-approximate-full-adder-for-real-time-edge-image-processing","status":"publish","type":"page","link":"https:\/\/els-journal.net\/wp\/?page_id=1070","title":{"rendered":"30201 Low Power CNTFET 3-Transistor Approximate Full Adder for Real-Time Edge Image Processing"},"content":{"rendered":"\n\n\n

Vol. 30, No. 2 – December 2026<\/h3>\n

Low Power CNTFET 3-Transistor Approximate Full Adder for Real-Time Edge Image Processing<\/h3>\n

https:\/\/doi.org\/10.53314\/ELS2630055S<\/h5>\n
Dasamandam Venkata Supriya and Avireni Srinivasulu<\/h5>\n
Abstract<\/b><\/h5>\n
A low-power 3-transistor (3T) approximate full adder based on CNFET technology is proposed for edge image processing <\/span>applications requiring low computational cost and compact<\/span><\/h5>
area. The design emphasizes high power efficiency through an ultra-minimal transistor structure, which reduces circuit complexity <\/span>while maintaining acceptable accuracy. Circuit-level performance <\/span>is evaluated using a 32 nm CNFET model in the HSPICE <\/span>simulator at a supply voltage of 0.9 V. The analysis considers key <\/span>metrics such as power dissipation, propagation delay, power-delay <\/span>product (PDP), and energy delay product (EDP). Results indicate <\/span>power savings of about 35\u201340% and a delay reduction of approximately <\/span>55\u201360% compared to conventional approximate adders. <\/span>Additionally, PDP improves by 75\u201380%, and EDP shows up to <\/span>90% enhancement. These improvements are mainly due to reduced <\/span>transistor count and simplified routing paths. Although the <\/span>design introduces approximation, the resulting accuracy remains <\/span>within acceptable limits for error-tolerant image processing tasks. <\/span>Overall, the proposed 3T CNFET full adder achieves an effective <\/span>balance between power, delay, area, and computational accuracy.<\/span><\/h5>\n
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