{"id":1022,"date":"2026-04-30T17:34:49","date_gmt":"2026-04-30T17:34:49","guid":{"rendered":"https:\/\/els-journal.net\/wp\/about\/"},"modified":"2026-04-30T18:02:12","modified_gmt":"2026-04-30T18:02:12","slug":"30103-finfet-based-computation-intensive-sub-circuits-designs-for-low-power-vlsi-application","status":"publish","type":"page","link":"https:\/\/els-journal.net\/wp\/?page_id=1022","title":{"rendered":"30103 FinFET Based Computation Intensive Sub-Circuits Designs for Low Power VLSI Application"},"content":{"rendered":"\n\n\n

Vol. 30, No. 1 – June 2026<\/h3>\n

FinFET Based Computation Intensive Sub-Circuits Designs for Low Power VLSI Application<\/h3>\n

https:\/\/doi.org\/10.53314\/ELS2630021G<\/h5>\n
Shyamosree Goswami, Nadegouni Sandeep, Dara Sai Kumar, and Anup Dandapati<\/h5>\n
Abstract<\/b><\/h5>\n
In order to improve operational efficiency for lowpower VLSI (Very Large Scale Integration) designs, the current research presents a simulation-based comparison of the results<\/h5>
of basic gates, computation-intensive circuits, and basic memory blocks designed using FinFET technology. This creative designs in <\/span>multipliers effectively consolidates input data by stacking blocks, <\/span>which significantly reduces time in next-stage operations. To <\/span>assess the suggested compressor design in terms of average power, <\/span>delay, and Power Delay Product (PDP), extensive simulations <\/span>and analyses are carried out. When conducted within the same <\/span>technological and environmental conditions as existing designs, <\/span>proposed designes demonstrate clear advantages. The proposed <\/span>compressor shows an amazing 64.91% decrease in delay, a significant <\/span>87.85% improvement in average power consumption, and <\/span>a notable 95.74% improvement in energy efficiency for proposed <\/span>4-3 compressor and similar outcomes for 5-3 compressor. In <\/span>memory design, it also demonstrates a notable enhancement, <\/span>achieving an 87.95% reduction in average power, a 49.57% <\/span>decrease in delay, and an 87.57% improvement in Energy Delay <\/span>Product (EDP) compared to both conventional NAND-based and <\/span>FinFET-based Content Addressable Memory (CAM) designs.<\/span><\/h5>\n
Full text: <\/a><\/h5>\n\n\n\n\n\"cited<\/a>\n\n\n\n\nGoogle Scholar Citations <\/a>\n\n\n\n\n
<\/span> <\/center>