Two-dimensional (2D) Convolution is frequently used in many image processing applications like image smoothening, image sharpening, feature extraction, image enhancement, object recognition, etc. Although the operation of 2D Convolution is simple, its hardware implementation is quite challenging due to enormous computational and memory costs. Various 2D convolution implementations have been proposed in the literature. Among them Separable architectures stand out in terms of the reduction in the computational complexity. However, these have not been extensively explored in the literature, and more research needs to be done, especially for applications that are constrained in resources. This paper presents a novel separable Convolution architecture based on the folding transformation. The application of the folding transformation technique yields a resource-efficient architecture by time multiplexing the different functional units within the separable Convolution operation. The hardware implementation is done using Xilinx Artix-7 xc7a35tcpg236-1 FPGA device. The proposed architecture offers benefits over the existing architectures regarding on-chip resource utilization, power consumption, critical path delay, and external memory bandwidth (EMB).